ONE HUNDRED AND TWO CITATIONS INDICATING OR HINTING AT
UNMANUFACTURABILITY AND/OR NON-PERFORMANCE IN NANOELECTRONICS RESEARCH
M J Kelly
These citations are in no particular
order, but the breadth of background indicates the seriousness of the problem
identified as intrinsic unmanufacturability, and suggests where the emphasis
for real impact of future research will lie.
There is also data stretching back 20 years on which manufacturability
advances have yet to be made. For every
citation here there are hundreds of papers which do not address the issue of
manufacturability at all!
[1]
A Asenov, A R Brown, J H Davies, S Kaya and G Slavcheva, ’Simulation of
intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs’,
IEEE Trans Elect. Dev., 50
1837-52 (2003)
‘Intrinsic
parameter fluctuations introduced by discreteness of charge and matter will
play an increasingly important role when semiconductor devices are scaled to
decananometer and nanometer dimensions in next-generation integrated circuits
and systems.’
[2] H. Fukutome, E. Yoshida, K. Hosaka, M.
Tajima,Y Momiyama, and S Satoh, ‘Effects of Gate Line Width Roughness
on Threshold-Voltage Fluctuation Among Short-Channel Transistors at High Drain
Voltage’ IEEE Electron Devices Letters 31 240-2 (2010)
‘The gate LER (line edge roughness) should
be a serious issue for reducing the variability among aggressively scaled
planar transistors.’
[3] G Fiol, D Arsenijević, D
Bimberg, A G Vladimirov, M Wolfrum, E A Viktorov, and Paul Mandel, ‘Hybrid mode-locking in a 40 GHz monolithic quantum dot laser’ Appl. Phys. Lett. 96 011104
(2010):
‘However, tailoring the characteristics of
quantum dot lasers for specific applications is a challenging issue’
[4] M J Kelly, ‘The unacceptable variability in tunnel currents for
proposed electronic device applications’ Semicon.
Sci. & Technol. 21 L49-L51 (2006), and references therein.
‘The engineering of tunnel barriers has not
yet succeeded to the point where low cost high volume manufacture of tunnel
devices can be undertaken.’
[5] A Bez and A Pirovano,’ Non-volatile memory technologies:
emerging concepts and new materials’ Mat. Sci. in Semicond.
Processing 7 349–355 (2004)
‘The current NVM (non-volatile memory)
mainstream is based on the Flash technology and it is expected that NOR and
NAND Flash will be the high volume NVM production for the rest of this decade.
Although the floating-gate concept has provided enthusiastic results, none of
the existing
and forecasted Flashmemory architecture is
able to optimize the entire performance set, which would bring it close to the
universal memory specifications.’
[6] Qi Zhong Yang, M J
Kelly, H Beere, I Farrer and G A C Jones, ‘The potential of split-gate transistors as one-dimensional electron
waveguides revealed through the testing and analysis of yield and
reproducibility’, Appl. Phys. Lett. 94
033502 (2009)
‘Although
many papers dealing with the physics in such systems have been published, there
have been rare systematic studies of the structure as a potentially
manufacturable device. Here we study its limitations through yield and
reproducibility testing and analysis. ‘
[7] C. Rutherglen, D. Jain and P. Burke,
‘Nanotube electronics for radiofrequency applications’ Nature
Nanotechnology 4, 811 - 819 (2009)
‘However, as it might not be possible to economically
manufacture the perfectly dense perfectly aligned arrays containing only
semiconducting nanotubes that are needed to achieve this level of performance,
it is important to benchmark trade-offs that result from using
less-than-perfect arrays.’
[8] L. Dai, ‘Aligned
carbon nanotubes for multifunctional nanocomposites and nanodevices: from
plastic optoelectronics to bioceramics ’
Adv. in Appl. Ceramics 107 177-89
(2008)
‘For
most of the above mentioned, and many other, applications, it is highly desirable
to prepare aligned/micropatterned carbon nanotubes and to modify their
surfaces, for example with polymers and metal (oxide) nanoparticles. Although a
large number of solution methods have recently been reported to modify nanotube
tips and sidewalls through either covalent or non-covalent chemistries, simple
application of the solution chemistry to the aligned carbon nanotubes, however,
could cause a detrimental damage to their alignment structure.’
[9] N. Srivastava and K.Banerjee, ‘Performance analysis
of carbon nanotube interconnects for VLSI applications’, Proceedings of the 2005 IEEE/ACM
International conference on Computer-aided design, 383-90 (2005)
‘The performance of CNT-bundle
interconnects has been compared to that of copper interconnects of future
technology generations and their applicability at different metal tiers in a
VLSI design is studied. At the local interconnect level, CNT-bundles with
imperfect contacts do not give much performance improvement.’
[10] Y Yang and R Murali, ’Impact of Size Effect on Graphene Nanoribbon Transport‘ IEEE Electron Device Letters 31 237-9 (2010)
‘The size
effect demonstrated in this work severely constrains the use of GNRs for
nanoelectronics applications unless methods are found to produce high-quality
GNRs.’
[11] A Boltasseva and V M Shalaev,’ Fabrication of optical negative-index
metamaterials: Recent advances and outlook’ Metamaterials 2 1-17 (2008)
‘Thus, this approach is only suitable for
proof-of-principle studies. Similar to electron beam lithography, other serial
processes, for example the focused-ion beam milling technique, are not
considered to be feasible for the large-scale metamaterial fabrication required
by applications. ‘
‘One approach
to manufacturing high-quality NIMs on a large scale (
[12] J-P Colinge, C-W Lee, A Afzalian, N Dehdashti Akhavan, R Yan, I
Ferain, P Razavi, B O’Neill, A Blake, M White, A-M Kelleher, B McCarthy and R
Murphy, ‘ Nanowire transistors without junctions’ Nature Nanotechnology 5
225-9 (2010)
‘We
find that the variability of the threshold voltage is larger in gated resistors
than in traditional ultrathin-film, inversion-mode SOI transistors.’
[13] Sven Rogge, ‘Single dopants learn
their place’, Nature Nanotechnology 5 100-1 (2010)
‘The presence of just one dopant atom can
dramatically alter the performance of a short-channel transistor, depending on
where it is located.’
‘Although single-ion implantation has been
achieved with an accuracy of about 10 nm using conventional top-down techniques
fluctuations in the performance of devices made using this method persist.’
[14] G. F. Jiao, Z. X. Chen, H. Y. Yu, X.
Y. Huang, D. M. Huang, N. Singh, G. Q. Lo, D.-L. Kwong, and Ming-Fu Li,
‘Experimental Studies of Reliability Issues in Tunneling Field-Effect
Transistors’, IEEE Electronic Device Letters 31 396-8 (2010)
‘We report, for the first time, the
reliability issues of tunneling
field-effect transistors (TFETs) by experiments. We observed that the overall
reliability performance of n-TFETs is very different from those of the
conventional n-MOSFET. The degradation of n-TFETs under positive bias
temperature instability (PBTI) stress is very large compared with the
negligible degradation for the conventional n-MOSFET. The degradation of
n-TFETs under hot-carrier stress is also larger than that in the conventional
n-MOSFET and has a different temperature dependence.’
[15] S Poli and M G Pala, ‘Channel-Length Dependence of Low-Field Mobility
in Silicon-Nanowire FETs’, IEEE Electron
Device Letters 30 1212-4 (2009)
‘Moreover, we have found an intrinsic
reduction of the low-field mobility for shorter channel lengths due to surface
roughness scattering independently of the role played by the apparent mobility
component. Both results contribute to explain the effective mobility reduction
observed in ultrashort electron devices.’
[16] M
Meneghini, U Zehnder, B Hahn, G Meneghesso and E Zanoni, ‘Degradation of
High-Brightness Green LEDs Submitted to Reverse Electrical Stress’, IEEE Electron Device Letters 30
1051-3 (2009)
‘The results of
this analysis indicated the following: 1) leakage current, due to a soft-breakdown
mechanism, flows through preferential localized paths and is strongly
correlated to the presence of reverse-bias luminescence; 2) reverse-bias stress
can determine an increase in the leakage current of the devices, with
subsequent decrease in the breakdown voltage and increase in the reverse-bias
luminescence; and 3) the degradation rate has a linear dependence on the stress
current and a superlinear dependence on the stress-voltage level. On the basis
of the results presented in this letter, degradation is attributed to the
generation/propagation of defects due to the injection of highly accelerated
carriers through defective sites.’
[17] R Wang, J
Zhuge, R Huang, D-W Kim, D Park and Y Wang, ‘Investigation on Self-Heating
Effect in Gate-All-Around Silicon Nanowire MOSFETs From Top-Down Approach’ IEEE Electron Device Letters 30
559-61 (2009)
‘With the multifinger and multiwire test
structure, the impact of the self-heating effect is successfully characterized.
The results indicate that even if the SNWT is fabricated on the bulk silicon
substrate, the impact of the self-heating effect is comparable or even a little
bit worse than that in SOI devices, probably due to the 1-D nature of nanowire
and increased phonon-boundary scattering in the GAA architecture.’
‘The extracted mobility-degradation factor
is an order of magnitude larger than those of other planar MOSFETs. This result
suggests that, while the all-around gate can turn off the electron channel.’
effectively, it creates more interface scattering
in the strong inversion condition.
[18] L Choi, B H
Hong, Y C Jung, K H Cho, K H Yeo, D-W Kim, G Y Jin, K S Oh, W-S Lee, S-H Song,
J S Rieh, D M Whang and S W Hwang, ‘Extracting
Mobility Degradation and Total Series Resistance of Cylindrical Gate-All-Around
Silicon Nanowire Field-Effect Transistors’, IEEE
Electron Device Letters 30 665-7 (2009)
‘The extracted
mobility-degradation factor is an order of magnitude larger than those of other
planar MOSFETs. This result suggests that, while the all-around gate can turn
off the electron channel effectively, it creates more interface scattering in
the strong inversion condition.’
[19] T
Matsukawa, K Endo, Y Ishikawa, H Yamauchi, i O’uchi, Y Liu, J Tsukada, K Ishii,
K Sakamoto, ESuzuki, and M Masahara, ‘Fluctuation
Analysis of Parasitic Resistance in FinFETs With Scaled Fin Thickness’, IEEE Electron Device Letters 30
407-9 (2009)
‘Measurement-based
analysis of the parasitic resistance (Rpara) of FinFETs was extended to
investigation of Rpara fluctuation, which could cause severe on-current
variation. Rpara was obtained from the intercept in the linear
relationship between measured on-resistance and gate length for FinFETs of
various dimensions. A significant increase in Rpara is observed for fin thickness
below 25 nm due to dopant loss from the ultrathin extension during processing. Rpara
variation was evaluated for 45 FinFETs with an average fin thickness of 16 nm.
Significant Rpara variation is observed and correlates with the
variation of fin thickness.’
[20] G Fiori and
G Iannaccone,’ On the Possibility of Tunable-Gap Bilayer Graphene FET, IEEE Electron Device Letters 30
261-3 (2009)
‘We explore the
device potential of a tunable-gap bilayer graphene (BG) FET exploiting the
possibility of opening a bandgap in BG by applying a vertical electric field
via independent gate operation. We evaluate device behavior using atomistic simulations
based on the self-consistent solution of the Poisson and Schrödinger equations
within the nonequilibrium Green’s function formalism. We show that the concept
works, but the bandgap opening is not strong enough to suppress band-to-band tunneling
in order to obtain a sufficiently large Ion/Ioff ratio for CMOS
device operation.’
[21] J-W Yang, H R Harris, G Bersuker, C Y Kang, J Oh, B H Lee, H-H Tseng and R Jammy, ‘New Hot-Carrier
Injection Mechanism at Source Side in Nanoscale Floating-Body MOSFETs’, IEEE
Electron Device Letters 30 54-6 (2009)
‘Hot-carrier
stress with accelerated gate voltage may lead to a huge overestimation of
lifetime in nanoscale floating-body MOSFETs.’
[22] A . Nozik,
‘Making the most of photons’ Nature Nanotechnology 4 548-9
(2009)
‘Time-resolved
spectroscopy has the potential disadvantage of exaggerating the MEG (multiple
exciton generation) quantum yield in the presence of unrelated phenomena, such
as direct photoionization and trapping. This has contributed to large
variations in reported MEG quantum yields, which, together with the lack of a
photovoltaic device with a quantum yield greater than unity, has led to some
scepticism in the community.’
[23] M
Prato, ‘Controlled nanotube reactions’, Nature
465 172-3 (2010)
‘Techniques for
modifying CNTs with organic chemical groups have been in development for many
years, but it is no exaggeration to say that the production of pure samples of functionalized
CNTs that are all of the same size is still the grand challenge for the field.
[24] E C
Garnett, Y-C Tseng, D R Khanal, J Wu, J Bokor and P Yang, ’Dopant profiling and
surface analysis of silicon nanowires using capacitance–voltage measurements’, Nature Nanotechnology 4 311-4
(2009)
‘A flat dopant
profile, such as is normally assumed using the standard method of estimating
the doping level from the measured conductivity, mobility and threshold voltage
cannot provide an accurate doping picture for our nanowires. These results unambiguously demonstrate that
quantitatively understanding and controlling the surface properties and dopant
distribution within semiconductor nanowires will be critical to achieve reproducible
high-performance devices.’
[25] D E Perea, E . Hemesath, E J
Schwalbach, J L Lensch-Falk, P W Voorhees and L J Lauhon, ‘Direct measurement
of dopant distribution in an individual vapour–liquid–solid nanowire’, Nature Nanotechnology 4 315-9
(2009()
‘Semiconductor nanowires show promise for
many device applications, but controlled doping with electronic and magnetic impurities
remains an important challenge. Limitations on dopant incorporation have been
identified in nanocrystals, raising concerns about the prospects for doping
nanostructures. Progress has been
hindered by the lack of a method to quantify the dopant distribution in single
nanostructures.
[26] M Steiner, M Freitag, V Perebeinos, J C
Tsang, J P Small, M Kinoshita, D Yuan, J Liu and P Avouris, ‘Phonon populations
and electrical power dissipation in carbon nanotube transistors’, Nature
Nanotechnology 4 320-4 (2009)
‘Carbon nanotubes and graphene are candidate
materials for nanoscale electronic devices. Both materials show weak acoustic
phonon scattering and long mean free paths for low energy charge carriers.
However, high-energy carriers couple strongly to optical phonons, which leads
to current saturation and the generation of hot phonons.’
[27] M T Björk, H Schmid, J
Knoch, H Riel and W Ries, Donor
deactivation in silicon nanostructures’ Nature Nanotechnology 4 103-7 (2009)
‘Electronic devices based on semiconductor nanowires will rely on
the location and number of dopant atoms in the host semiconductor being controlled
during the fabrication process. It has now been shown that the properties of
dopant atoms — in particular, their ionization energies — change with nanowire
radius more markedly than previously predicted.’
[28] A A Green and M C Hersam, ‘Processing and
properties of highly enriched double-wall carbon nanotubes’, Nature Nanotechnology 4 63-70
‘Carbon
nanotubes consist of one or more concentric graphene cylinders and are under
investigation for a variety of applications that make use of their excellent thermal,
mechanical, electronic and optical properties. Double-wall nanotubes are ideal
systems for studying the interwall interactions influencing the properties of
nanotubes with two or more walls. However, current techniques to synthesize
double-wall nanotubes produce unwanted single- and multiwall nanotubes.’
[29] G Xu, F Liu, S Han, K Ryu, A Badmaev, B Lei, C Zhou and
K L Wang, ‘ Low-frequency noise in
top-gated ambipolar carbon nanotube field effect transistors, Applied Physics
Letters 92, 223114, (2008)
‘However, the
CNT synthesis on the Si/SiO2 substrate normally cannot control the CNT growth
direction and the device structure has large parasitic capacitances, which
limits their use for manufacturable CNT integrated circuits.
[30] V C Tung, M J Allen, Y Yang and R B
Kaner, ‘High-throughput solution processing of large-scale graphene’, Nature
Nanotechnology 4 25-9 (2009)
‘However, it is still difficult to produce
single-layer samples of graphene, and bulk processing has not yet been
achieved, despite strenuous efforts to develop a scalable production method.’
[31] C D Presti, A Irrera, G Franzò, I Crupi
and F Prioloa, ‘Photonic-crystal
silicon nanocluster light-emitting device’ Applied
Physics Letters 88,
033501 (2006)
‘Nevertheless, device performance has still
to be improved to meet application requirements.’
[32] Y-C Lin, C-Y Lin and P-W Chiua, ‘ Controllable graphene N-doping with ammonia plasma’ Applied Physics Letters 96,
133110 (2010)
‘This approach preserves the carbon network from
being severely damaged but the rapid degradation upon exposure to air sets the
fundamental constriction for its practical applications. Therefore, graphene
functionalization by various inorganic or organic substances, which provides
airstable dopant and permanently alters the electronic structure of graphene
sheets, has been of emerging importance in this respect. Adsorption of various
organic molecules has revealed the extreme sensitivity of the electrical
properties of graphene to molecule species.8 However, the precise control over
the adsorption coverage and the sustainability at high processing temperature
remain challenged for the noncovalent functionalization.’
[33] B Georges, J Grollier, V Cros and A Fert, ‘Impact of the electrical connection of spin
transfer nano-oscillators on their synchronization: an analytical study’ ,
Applied Physics Letters, 92, 232504 (2008)
‘Due to their tunability, high frequency
emission, quality factor, and high level of integration, spin transfer nano-oscillators
(STNOs) are promising candidates for applications in future wireless
telecommunications. Nevertheless a major breakthrough has to be performed
related to their low emitted power, typically less than 1 nW.’
[34] D Lu, J Ahn, S Freisem, D Gazula and D
G Deppea, ‘ Lens-shaped all-epitaxial quantum dot microcavity’, Applied Physics Letters 87,
163105 (2005)
Although QD nanophotonics could lead to new
technologies based on spontaneous quantum light sources and ultra-low-power,
high-speed QD lasers, present semiconductor microcavities have serious
drawbacks for practical applications. Perhaps most daunting are the fragilility
and poor thermal conductivity that result from thin-film photonic crystals, whispering
gallery microdisks, or etched pillars. Oxide confinement suffers poor
controllability, making it impractical. Electrical injection in these
microcavities is also difficult, if not impossible, especially because of the
thin layers.
[35] J E Jang, S N Cha, Y Choi, G A Amaratunga, D J Kang, D G Hasko,
J E Jung and J M Kim, ‘Nanoelectromechanical switches with vertically
aligned carbon nanotubes’, Applied
Physics Letters 87, 163114 (2009)
‘The fabrication of nanoelectromechanical
systems (NEMS) has recently been a highly active area of research as it holds
great promise for a number of scientific and technological applications. Until
now, most NEMS have been typically fabricated by high-resolution lithographic
and etching techniques. However,
developing a reproducible and routine nanofabrication method suitable for NEMS
by these processes is still far from realization due to much stringent
processing conditions.’
[36] K Meneou, K Y Cheng, Z H Zhang, C L Tsai,
C F Xu and K C Hsieh ‘Site-controlled InAs quantum dots regrown on
nonlithographically patterned GaAs’ Applied
Physics Letters 86, 153114 (2005)
‘The most widely used approach for the
fabrication of dense arrays of QDs is epitaxial growth in the
Stranski-Krastanow growth mode, especially in the InAs-on-GaAs material system. This approach yields dense arrays of self-assembled
QDs of high optical quality, and has been used to demonstrate QD lasers and
other optical devices. The limitations of this approach are the lack of control
over QD spacing and QD size distribution. The QDs are typically randomly
arranged in the plane of the QD layer, and are of nonuniform size, leading to
nonuniform optical properties of the QD array.’
[37] A Knübel, V M Polyakov, L Kirste and R Aidam, ‘Nonuniformity of
electron density in In-rich InGaN films deduced from electrolyte
capacitance-voltage profiling’ Applied Physics Letters 96,
082106 (2010)
‘A strong electron accumulation at InN and
In-rich InGaN surfaces remains the main drawback that seriously hinders a
further progress in manufacturing electron devices such as field-effect transistors
where metal gates to these materials are required. The electron accumulation is
caused by a downward band bending at the surface, attributed to donor-like
surface states, which pin the Fermi level at the surface well above the
conduction band edge.’
[38] K Kim, P C
Debnath, D-H Park, S Kim, and S Y Lee, ‘Controllability
of threshold voltage in Ag-doped ZnO nanowire field effect transistors by
adjusting the diameter of active channel nanowire’, Applied Physics Letters 96, 083103 (2010);
‘The interface roughness is important in
thin film transistors (TFTs) and general
metal-oxide semiconductor field effect transistors (MOSFETs) in terms of scattering.8
Similarly, the electronic transport in NW transistors can be influenced by
changing the NWs diameter, such as the thickness of the active channel layer.9
In addition, the properties on nanostructures used as building blocks for the assembly
of nanoscale device strongly depend of their shape and size. Moreover, despite many researches on charge transport
in ZnO-based materials the size-and surface morphology-dependent effect on the
electronic transport on NWs with corrugated shapes have rarely been reported. ‘
[39] J Li, HY Yu, S M Wong, X Li, G Zhang, P
G-Q Lo and D-L Kwong, ‘Design guidelines of periodic Si nanowire arrays for
solar cell application’ Applied
Physics Letters 95, 243113 (2009)
‘Recently, the impact of the SiNW length (L)and
diameter (D) on the optical characteristics of the SiNW arrays is
reported based on a fixed array periodicity (P) of 100 nm.12 The
simulation results show that the excellent light absorption close to 100% is
achievable in the high energy region of the solar spectrum (2.8 eV), in
agreement with the experimental results.9,10 It further indicates that the
total solar energy harvesting of the SiNW arrays in the energy region of 1–4
eV, covering the major energy range of the solar spectrum, is lower than that
of the Si thin film with the same thickness due to the poor light absorption in
the low energy region of the solar spectrum (2 eV), though it is observed that
the light trapping capability can be improved with the SiNW diameter. ‘
[40] K W Chiu Lai, N Xi, C K M Fung, H Chen
and T-J Tarn, ‘Engineering the band gap of carbon nanotube for infrared sensors’,
Applied Physics Letters 95,
221107 (2009)
‘Classical band gap materials are inherently
limited by their atomic and lattice structures. However, the electron transport
in a carbon nanotube (CNT) is confined to one dimension and the wave function
has a periodicity in the circumferential direction, so the band gap of a CNT is
determined by its diameter and chirality. If the diameter of a CNT increases,
more wave vectors are allowed in the circumferential direction and thus the
band gap of the CNT decreases. It is
known that the diameter of CNTs is inversely proportional to the band gap and
CNTs have been used to produce nanotransistors and infrared detectors. However,
the band gap of the current CNT varies in a wide range and it makes the
realization of a practical CNT-based device difficult.’
[41] JI Lee, Y H Jeong, H-C No, R Hannebauer, andbS-K Y,
‘Size effect of nanometer vacuum gap thermionic power conversion device with
CsI coated graphite electrodes’ Applied Physics Letters 95,
223107 (2009)
‘Cesium iodide (CsI) coated graphite is a
good candidate for an electrode material of a thermionic power generation
device due to its low work function. In this letter, a thermionic device with a
nanometer-scale vacuum gap between a CsI coated graphite emitter and a
collector will be investigated while considering various gap-size effects. It
is shown that a nanometer scale gap-size not only affects electron transport
but also photon transport, and that all of these effects must be taken into
account when estimating the device’s performance. ‘
[42] M Haselman and S Hauck, ‘The
Future of Integrated Circuits: A Survey of Nanoelectronics’, Proceedings of the IEEE 98 11-38 (2001)
‘As can be seen, a substantial amount of
research has been conducted on nanoelectronics. Many working devices have been
designed and fabricated, along with a number of small-scale memory chips, but
there are some big hurdles to overcome. These hurdles include lowering defect
levels to a point that reasonable redundancy levels can be used, integrating
billions of devices, and developing software tools to complement the new
technologies. However, the prospect of cheaply integrating 1012
devices per chip is a powerful incentive to overcome the challenges.’
[42] R Chau, S Datta and A Majumdar, ‘Opportunities and Challenges
of III-V Nanoelectronics for Future High-Speed, Low-Power Logic
Applications’ Compound Semiconductor Integrated
Circuit Symposium, 2005. CSIC '05. IEEE, 17-20 (2005)
‘III-V quantum-well
transistors still have many difficult challenges that need to be overcome before they can be considered useful for logic applications….Schottky
gate leakage for want of good dielectric, …. p-channel FETs with very high hole mobility
for logic applications, … III-V materials will need to be integrated
selectively onto the Si platform.’
[43] K Galatsis, R Potok and K L Wang, ‘A
Review of Metrology for Nanoelectronics’, IEEE
Transactions on Semiconductor Manufacturing, 20 542-8 (2007)
‘The MOSFET itself has been theoretically
shown to operate at the fundamental limit of kTlog2 as derived by the
ideal MOSFET model by Swanson and Meindl in 1971. However, for the industry to
have any chance at reaching these ultimate limits with high yields and without
economic exorbitance, materials and manufacturing processes must also be ideal,
materials need to be pristine, defects completely eliminated, geometries
patterned within atomic precision, and dopants positioned with 3-D atomic
control. To achieve such excellence, technological development would be
required in the following areas: 1) advanced materials; 2) sophisticated
fabrication tools and processes; and 3) integrated metrology tools and
modeling.’
[44] K Sivakumar and B Panchapakesan, ‘ Electric
Field Assisted Deposition of Nanowires from Carbon Nanotubes for Nanoelectronics
and Sensor Applications, Proceedings of
the International Conference on MEMS, NANO and Smart Systems (ICMENS’03) 203 –
208 (2003)
‘There are numerous techniques that have
been developed for the synthesis of nanowires. These include molecular beam
epitaxy, chemical vapor deposition, solution phase approach, electrochemical
approach, pyrolysis, selective deposition and chemical etching, laser ablation,
focused ion beam writing, proximal probe patterning, X-ray and deep UV
lithography and oxide assisted catalyst free methods …. However, further
development of these techniques into practical routes to large quantities of
1-D nanostructures from a diversified range of materials, rapidly and at reasonably
low cost requires ingenuity.’
[45] R I Bahar, D Hammerstrom, J Harlow, W H
Joyner Jr., C Lau, D Marculescu, A Orailoglu and M Pedram, ‘Architectures for Silicon
Nanoelectronics and Beyond ‘, Computer
40 25-33 (2007)
‘Projected nanodevice manufacturing
processes will be radically different from conventional CMOS processes, at
least in the case of bottom-up manufacturing. Because they’re still in their
infancy, the manufacturing precision is low, resulting in significant
statistical variability of each device’s key physical, chemical, and electrical
properties. These phenomena are exacerbated because the complex and highly
controlled patterns that photolithography enables will likely be impractical
for nanoelectronic fabrication. Because
of their very small scale, these devices will be susceptible to various kinds
of noise, including energy coupling, temperature variations, and single-event upsets.
Finally, our limited ability to see what’s happening at that scale will make
failure analysis extraordinarily difficult.’
[46] S
Lazarova-Molnar, V Beiu, and W Ibrahim, ‘Reliability: the fourth optimisation
pillar of nanoelectronics’, IEEE International Conference on Signal Processing
and Communications (ICSPC 2007) 24-27 (2007)
‘The expectations are that the future
nano-circuits will exhibit higher frequency of failures. The higher density of transistors
on chip is one of the reasons for this behavior. Other factors that impact the
reliability are the geometric variations and manufacturing defects.’
[47] W Liu, J J Liou, Y Jiang, N Singh, G Q
Lo, J Chung and Y H Jeong, ‘Investigation of Sub-10-nm Diameter,
Gate-All-Around Nanowire Field-Effect Transistors for Electrostatic Discharge
Applications’ IEEE Transactions on
Nanotechnology 9 352-4 (2010)
‘Considered as one of the promising
next-generation nanostructure devices, the Si gate-all-around nanowire field-effect
transistor (NWFET) has been studied extensively in recent years. Research
efforts have so far focused on theNW FET fabrication and characteristics, and
the electrostatic discharge (ESD) tolerance and robustness of these devices
subject to the ESD events are still not well understood. ESD is an event in
which the charge is transferred from one object with a higher potential to
another object with a lower potential. About 35% of all damaged microchips, integrated
circuits, and devices are ESD related. As the CMOS technology is advancing toward
the 10-nm feature size, the availability of effective ESD protection solutions
becomes increasingly important and challenging.’
[48] R-H Baek, C-K Baek, S-W
Jung, Y Y Yeoh, D-W Kim, J-S Lee, D M Kim and Y-H Jeong,, Characteristics
of the Series Resistance Extracted From Si Nanowire FETs Using the Y -Function
Technique’, IEEE Transactions on
Nanotechnology 9 212-7 (2010)
‘However, the variations of Rsd
is shown rather high amounting to about 50% of the average values, thereby
indicating that the process parameters used for the contact formation vary
considerably from device to device.’
[49] G Ali, M Ahmad, J I Akhter, K Maaz, S Karim, M Maqbool and S G Yang, ‘Characterization of Cobalt Nanowires
Fabricated in Anodic Alumina
Template Through AC
Electrodeposition,
IEEE
Transactions on Nanotechnology 9 223-8 (2010)
‘The observed increase in coercivity, in
this case, may be due to the two different reasons. First, the coercivity
difference in nanowires is due to many different factors including crystallinity
of the nanowires and individual nanograins, their orientations within the
nanowires, as well as the morphological changes of the nanowires. Second, it
may be due to the inner spins of the nanowires that may lag behind the surface spins
during magnetization reversal when the applied field is reversed, resulting in
the increasing value of coercivity of the nanowires.’
[50] E-S Liu, N Jain, K M Varahramyan, J
Nah, S K Banerjee and E Tutuc, ‘Role of Metal–Semiconductor Contact in Nanowire Field-Effect
Transistors’, IEEE Transactions on
Nanotechnology 9 237-42(2010)
‘For example, the Schottky-barrier (SB)
height of a metal/CNT contact is determined by the metal work function, as well
as by the CNT diameter. In the case of semiconductor NWs, a statistical study
of the resistance of Si NW FETs with metal contacts shows a
two-order-of-magnitude-wide distribution.’
[51] J J-Y Kuo, W P-N Chen and P Su,’Investigation
and Analysis of Mismatching Properties for Nanoscale Strained MOSFETs’, IEEE Transactions on Nanotechnology 9
248-53 (2010)
‘With the scaling of device dimensions, the
device mismatching that stems from stochastic fluctuations is becoming a concern
for nanoscale MOSFETs. Device mismatch may limit the achievable accuracy in
analog applications such as multiplexed analog systems, digital-to-analog converters,
reference source, and the synchronous RAM (SRAM), etc.’
[52] S Harrer, S Strobel, G P Blanco, G
Scarpa, G Abstreiter, M Tornow and P Lugli, ‘Technology Assessment of a Novel
High-Yield Lithographic Technique for Sub-15-nm Direct Nanotransfer Printing of
Nanogap Electrodes, IEEE Transactions on
Nanotechnology 8 662-70 (2009)
‘High contact pressure in a “hard-on-hard”
mold–substrate arrangement during nTP (nanoscale transfer printing) cycles
yields a high mold wear. Additionally, since no flexible interface layer
exists, even slightest particle contamination of the mold–substrate interface
causes mold features either to bend, break, or not be in physical contact with
each other. Therefore, our best direct nTP results show a pattern transfer
efficiency of ∼80%, i.e.,
approximately 80% of the coated total mold pattern area is transferred onto the
substrate in each nTP experiment and ∼80% of all mold
structures are well preserved during the process.’
[53] B H Hong, Y C Jung, J S Rieh, S
W Hwang, K H Cho, K H Yeo, S D Suk, Y Y Yeoh, M. Li, D-W Kim, D
Park, K S Oh and W-S Lee, Possibility of Transport Through a Single
Acceptor in a Gate-All-Around Silicon Nanowire PMOSFET, IEEE Transactions on Nanotechnology 8 713-7 (2009)
‘Rapid scaling of MOSFETs has led us into a regime where counting
individual dopants (donors and acceptors) as well as individual oxide charges is important in determining the threshold
voltage of each device. The threshold voltage is not the quantity determined
from the average doping density any more, and there is an appreciable device to-
device fluctuation due to irregular distribution of individual dopants. As the
device size becomes even smaller, we encounter a device whose characteristic is
determined completely by the existence of a single impurity in the channel.
Recently, various transport studies regarding such single-dopant effects have
been reported [5]–[8]. In the case of nanowire devices, a single impurity in
the channel will also strongly affect the characteristics of the whole device
because the impurity, no matter where it exists in the length direction, can
easily influence the entire current flow.’
[54]
Z L Martin, N Majumdar, M J Cabral, N Gergel-Hackett, F Camacho-Alanis,
N Swami, J C Bean, L R Harriott, Y Yao, J M Tour, D Long and R.
Shashidhar, ‘Fabrication and Characterization of Interconnected Nanowell
Molecular Electronic Devices in Crossbar Architecture’, IEEE Transactions on Nanotechnology 8 574-81 (2009)
‘The implementation of circuit architectures
based on molecular electronic devices has been impeded by the availability of
facile fabrication schemes for the interconnection of individual devices. The
deposition and patterning of a top contact layer between adjoining devices for
interconnection purposes can result in contacts of poor fidelity, which
introduces artifacts in the I–V characteristics that are not
attributable to molecular transport between the contacts.’
[55] A
D Franklin, R A Sayer, T D Sands, D B Janes and T S Fisher, ‘Vertical
Carbon Nanotube Devices With Nanoscale Lengths Controlled Without Lithography’,
IEEE Transactions on Nanotechnology 8
469-76 (2009)
‘The unique properties of single-walled
carbon nanotubes (SWCNTs), such as 1-D electrostatics and equal electron and
hole effective masses, make them ideal for many nanoelectronic applications,
from interconnects to FETs. With ballistic transport attainable and high
current-carrying capacity, SWCNTs could enable the fastest and most robust
electronics to date. However, as with most nanomaterials studied in the last decade,
control of the placement and addressability of SWCNTs still precludes their
integration in practical applications. Recent progress has been reported on the
planar alignment of SWCNTs on a substrate via directed growth techniques
[1]–[3], which offer improved control over the SWCNTs directionality; however, definition
of the lateral density of the planar SWCNTs remains a challenge, with a best
reported controlled density to date of ten SWCNTs per linear micrometer [2].
Also, as the SWCNTs be-come more densely packed, the spacing between them
becomes less controlled [3], and the final devices can suffer from
inhomogeneous charge screening effects between the SWCNTs [4], [5]. Furthermore,
control of SWCNT length, which would serve as the channel length in a
self-aligned FET, still requires advanced lithographic processes with high
costs and low throughput that are not amenable to large-scale integration.’
[56] D S Lee, S Kang, K-C Kang,
J-E Lee, Jung Hoon Lee, K-J Song, D M Kim, J D Lee and
B-G Park, ‘Fabrication and Characteristics of Self-Aligned Dual-Gate
Single-Electron Transistors’, IEEE
Transactions on Nanotechnology 8 492-7
(2009)
‘Single electron transistors (SETs) are
considered as one of the promising devices for future ultralow power and high-density
systems. Especially, silicon based SETs have advantages in the fabrication and
design of CMOS/SET hybrid circuits. Due to its potential, it has been
actively investigated by many researchers, and various structures have been
introduced. However, low operation temperature and poor fabrication
controllability still remain as obstacles to practical application.’
[57]
N Patil, A Lin, E R Myers, K Ryu, A Badmaev, C Zhou, H-S P
Won, and S Mitra, ‘Wafer-Scale Growth and Transfer of Aligned Single-Walled
Carbon Nanotubes’, IEEE Transactions on
Nanotechnology 8 498-504 (2009)
‘The measured current is due to the CNTs
bridging the contacts and provides a measure of the electrical uniformity of
the CNTs across the wafer. Fig. 8 shows the mean current and the standard
deviation of these two terminal measurements at a bias of 1V. The standard
deviation of CNT current equals to ∼25% of the mean
current in all regions. The variation in CNFET current is likely due to
variation in the CNT density and CNT contact resistance.’
[58] T
Kaizawa, M Arita, A Fujiwara, K Yamazaki, Y Ono, Hiroshi Inokawa,
Y Takahashi and J-B Choi, ‘Single-Electron Device With Si Nanodot
Array and Multiple Input Gates‘, IEEE
Transactions on Nanotechnology 8 535-41
(2009)
‘ Recent progress in nanofabrication
technologies has made it possible to fabricate small metal-oxide semiconductor field-effect
transistors (MOSFETs) and highly integrated circuits (ICs). Although small FETs
have high performance such as high current drivability, their further
integration is limited by their power dissipation. In addition, when the
feature size is close to 10 nm, various types of fluctuations arise from the random
distributions of, for example, surface or interface roughness, impurities, and
line edge roughness. Moreover, the atomic-scale fluctuations cannot be
controlled, which is a significant problem for scaling down Si MOSFETs.’
[59] V Varadarajan, L Smith, and T-J
K Liu, ‘FinFET Design for
Tolerance to Statistical Dopant Fluctuations’, IEEE Transactions on Nanotechnology 8 375-8 (2009)
‘Nonclassical transistor structures are attractive for extending
CMOS technology scaling because of their superior immunity to short-channel
effects (SCEs) and higher carrier mobilities as compared to the classic bulk-Si
MOSFET [1]. The FinFET is a promising structure because it offers the superior
scalability of the double-gate structure together with a fabrication process
and layout similar to that of the conventional bulk-Si MOSFET. An undoped
channel is desired to eliminate VT variations due to statistical dopant
fluctuation (SDF) effects in the channel and to attain the highest possible
carrier mobilities to achieve high performance (ON-state drive current ION).
However, the device is still prone to random variations caused by SDF in the
source and drain (S/D) regions and gate/fin line-edge roughness, which can be
significant for very small gate lengths.
[60] M Stanisavljevic, A Schmid and Yf Leblebici, ‘Optimization
of the Averaging Reliability Technique Using Low Redundancy Factors for
Nanoscale Technologies, IEEE Transactions
on Nanotechnology 8 379-90
(2009)
‘The
technology scaling that has been the trend for decades is expected to continue
at the same speed or possibly at a slightly slower pace for at least the next
ten years. The nanoage has already begun, where typical feature dimensions are
considered to be less than 100 nm. The operation frequency is expected to
increase up to 12 GHz, and a single chip will contain over 12 billion
transistors in 2020. Future very-deep submicrometer and nanoelectronic
fabrication technologies are expected to suffer from the dramatic dimensional
scaling, which will impact on the proper operation of individual transistors, showing
up as current leakage, hot electron degradation, and device parameter
fluctuations. Moreover, future systems based on nanoelectronic devices are
assumed to suffer from low reliability due to both permanent and transient
errors. Permanent error rate will increase due to constraints imposed by
fabrication technologies. Transient errors rate will increase due to
nondeterministic parasitic effects such as background charge, which may disrupt
correct operation of single devices both in time and space in a random way.
Higher frequencies pose strict limits to timing, and therefore also add the
probability of timing errors as well.’
[61] T Wang, P Narayanan and C A Moritz, ‘Heterogeneous Two-Level Logic and Its
Density and Fault Tolerance Implications in Nanoscale Fabrics’, IEEE Transactions on Nanotechnology 8 22-30 (2009)
‘Integrating nanodevices into computing
systems is facing new challenges not encountered in conventional CMOS. Self-assembly-based
manufacturing imposes doping/layout constraints on nanoscale circuits,
restricting routing and placement.’
[62] Yi
Shan, A K Kalkan, C-Y Peng and S J Fonash, ‘From Si Source Gas Directly to Positioned,
Electrically Contacted Si Nanowires: The Self-Assembling “Grow-in-Place”
Approach, Nano Letters 4 2085-9 (2004)
‘While the
growth of nanowires has received considerable study, a
manufacturable approach to the assembly of nanowires into nanoscale
devices and circuits, required to enable nanoelectronics
and photonics,6 is much less developed. “Pick-and-place”
methods have been tried for many types of nanowire
materials, including Si, but these methods are very
time-consuming and arduous. Solution and
dry printing methods have also been tried and have proven to be most
effective for Si when dry printing an aligned block of SiNWs onto
plastic. In this case, aligned SiNWs are
constructed on SOI wafers by traditional silicon fabrication and then dry
printed onto a plastic substrate. Alignment and positioning are inherent to
this approach, but issues such as SOI wafer cost and effective, reproducible
contact welding to pads on the plastic remain. A third method, closest to our grow-in-place
approach, uses prepositioned catalysts and electric fields to do the self
assembling/self-positioning However,
this method, demonstrated for carbon nanotubes, has no control over the number
of tubes at a site and the nanotube alignment varies. Clearly, semiconductor
nanowire devices and circuits will not realize their full potential until these
various issues are solved and an economically feasible, manufacturable approach
to nanowire growth, positioning, number at a position, orientation, contacting,
and passivation is developed.’
[63] E
Artukovic, M Kaempgen, D S Hecht, S Roth and G. Gru1ner,
‘ Transparent and Flexible Carbon
Nanotube
Transistors’, Nano Letters 5
757-60 (2005)
‘The quest for
flexible and transparent transistors has recently resulted in several
noteworthy achievements. Transparent transistors have been fabricated using
both polymers and inorganic oxides. These advances, notable in the emerging technology
arena that is generally called “plastic electronics”, have received wide
publicity. Both, nevertheless, have significant deficiencies. The former have
low mobility and the latter do not have the desired flexibility and are not
easily manufacturable. These factors severely limit the application potential
of the devices.’
[64] A Chaudhry,
V Ramamurthi, E Fong and M S Islam, ‘ Ultra-Low Contact Resistance of Epitaxially
Interfaced Bridged Silicon Nanowires’, Nano
Letters 7 1536-41 (2007)
‘A significant
roadblock to wide-scale integration of functional nanowire-based devices is the
difficulty in forming contacts to the nanowires. A scheme aimed at integrating nanowires in
devices and circuits should be universal, compatible with current IC processing
methods, and cost-effective. In addition, precise control on the nanowire
length, reliable and low contact resistance, and good mechanical robustness
will be highly desirable. To date, many reported techniques for fabricating
nanowires in controlled and reproducible fashion did not meet most of the
above-mentioned requirements and a dramatically new approach is needed for
integrating nanowires with conventional circuitry.’
[65] Q Ngo, B A
Cruden, A M Cassell‡ G Sims, M Meyyappan, J Li and C Y Yang, ‘Thermal Interface
Properties of Cu-filled Vertically Aligned Carbon Nanofiber Arrays’, Nano Letters 4 2403-7 (2004)
‘Thermal
characteristics of multiwall carbon nanotubes (MWNTs) have been measured,1-4
revealing their unique thermal conductivity characteristics along the nanotube
axis. For a discrete MWNT, thermal conductivity has been measured surpassing
3000Wm-1 K-1 in the axial direction.1 Other studies have reported values for
discrete MWNTs as small as 15 (W m-1 K-1) and 27 (W m-1
K-1). The wide variation can be attributed to the inherently
disordered nature of some carbon nanostructures grown by the chemical vapour deposition
(CVD) process. Concerns about the degradation of thermal conductivity in
vertically aligned carbon nanofiber (VACNF) arrays due to poorly graphitized
structures are valid when considering these structures in thin film
applications where the intrinsic film properties are of great importance. In
cases of studying thermal contact resistance, however, the physical nature of
the contact between the nanofiber ends and hot contact surface tends to take precedence.’
[66] G
S.McCarty, ‘Molecular Lithography for Wafer-Scale Fabrication of Molecular
Junctions’, Nano Letters 4
1391-4 (2004)
‘More recently, novel techniques have been
developed for patterning surfaces with extremely high resolution. These
techniques include directly writing patterns onto a surface using the tip of a scanning
probe microscope, selective etching processes for line formation, and the
utilization of molecular layers as lift-off resists. The best resolutions
reported with any of these techniques are on the order of 8 to 10 nm. Improvements
are needed to increase the patterning resolution to only a few nanometers, the
approximate size of a single molecule.’
[67] G-Y Jung, E
Johnston-Halperin, W Wu, Zh Yu, S-Y Wang, W M Tong,| Zhiyong Li, J . Green, B A
Sheriff, A Boukai, Y Bunimovich, J R Heath and R S Williams, ‘ Circuit
Fabrication at 17 nm Half-Pitch by Nanoimprint Lithography, Nano Letters 6 351-4 (2006)
‘Features in a
superlattice structure with a less than 15 nm half-pitch have been previously
patterned on a polymer resist by nanoimprint lithography. However, transferring such patterns from the
imprinted resist to the substrate as metal wires is far more difficult and
until now has not been reported. Imprinting ultradense patterns poses several
additional challenges. For example, issues such as the thickness of the imprinting
resist, resist adhesion to the mold features, composition of the resist
material and the selectivity of various etching processes, etc., all require
higher levels of control than are needed for less demanding replication tasks.’
[68] C C Wu, C H
Liu and Z Zhong, ‘ One-Step Direct Transfer of Pristine Single-Walled Carbon
Nanotubes for Functional Nanoelectronics’, Nano Letters 10 1032–1036 (2010)
‘Conventionally,
SWNT nanoelectronic and nanophotonic devices are fabricated through either
postgrowth fabrication or postfabrication growth approaches. For the postgrowth
fabrication method, SWNTs are first placed onto a device substrate by either
direct chemical vapor deposition (CVD) growth or indirect solution process.
Lithography is then carried out to define the functional devices. This method
is widely adopted, yet SWNTs are inevitably contaminated by organic residues
resulting from the lithography and solution processing. To eliminate
contaminations, a postfabrication growth method is developed to avoid solution processing.
Lithography is carried out first to define electrical contacts made out of high
melting temperature metals (such as platinum). SWNTs are subsequently grown directly
on top of the electrodes by CVD method. This technique results in ultraclean
SWNT devices, but the high growth temperature (∼900 °C) prohibits its wide applications. More recently, SWNTs grown on
substrate were also shown to be transferred onto electrodes by stamping. However, potential contamination and damages
to SWNTs can come from the stamping process, and the registry of SWNTs to the
electrodes is entirely random.’
[69] Y-F Lin and
W-B Jian, ‘The Impact of Nanocontact on Nanowire Based Nanoelectronics’ Nano
Letters 8 3146-50m(2008)
‘Nanowire-based
nanoelectronic devices will be innovative electronic building blocks from
bottom up. The reduced nanocontact area of nanowire devices magnifies the
contribution of contact electrical properties. Although a lot of
two-contact-based ZnO nanoelectronics have been demonstrated, the electrical
properties bringing either from the nanocontacts or from the nanowires have not
been considered yet. High quality ZnO nanowires with a small deviation and an average
diameter of 38 nm were synthesized to fabricate more than thirty nanowire devices.
According to temperature behaviors of current-voltage curves and resistances,
the devices could be grouped into three types. Type I devices expose thermally
activated transport in ZnO nanowires and they could be considered as two Ohmic
nanocontacts of the Ti electrode contacting directly on the nanowire. For those
nanowire devices having a high resistance at room temperatures, they can be
fitted accurately with the thermionic-emission theory and classified into type
II and III devices according to their rectifying and symmetrical
current-voltage behaviors. The type II device has only one deteriorated
nanocontact and the other one Ohmic contact on single ZnO nanowire. An
insulating oxide layer with thickness less than 20 nm should be introduced to
describe electron hopping in the nanocontacts, so as to signalize one and high-dimensional
hopping conduction in type II and III devices.’
[70] Y Peng, T
Cullis, and B Inkson, ‘ Bottom-up Nanoconstruction by the Welding of Individual
Metallic Nanoobjects Using Nanoscale Solder’, Nano Letters 9 91-6 (2009)
‘A number of
localized joining methods suitable for individual nanoscale objects have
recently been proposed including thermal heating, ion beam deposition of material,
laser heating, ultrasonic irradiation, high-energy electron beam bombardment, and Joule heating from electrical currents. Of
these the method of Joule heating may hold the most potential because of its
formation of electrically conducting junctions, inherent simplicity,
cleanliness, and reliability. The other methods suffer from a number of
problems for practical industrial application. For example, high-energy
electron beam systems are expensive and are not easily integrated into
industrial production lines. Focused ion beam-based deposition currently only
has limited chemistries with poor control of functionality and contamination, and
thermal heating methods have very poor spatial control of heated zones and
contamination.’
[71] A L
Schmitt, L Zhu, D Schmeiâer, F J Himpsel, and S Jin, ‘Metallic Single-Crystal CoSi Nanowires via
Chemical Vapor Deposition of Single-Source Precursor, Journal of Physics Chemistry B 110 18142–6 (2006)
‘To acquire a
better statistical survey of the transport properties of CoSi nanowires, we
employed photolithography methods to produce a large number of addressable
devices. The calculated resistance values for a collection of of these two-terminal devices are displayed in
a logarithmic histogram [Ranging from 1 to 50W: MJK]. Deviation from peak resistance is due to the
range of nanowire diameters grown, differences in channel lengths from the
random orientation of nanowires across the fixed electrode gaps, and a certain
probability of multiple wire devices, which is consistent with our large scale
device fabrication scheme. We determined the average resistivity of our CoSi
nanowires to be 510mWcm using data from 35 single nanowire
devices for which diameter, channel length, and single connectivity were
established by SEM. This value is within the (surprisingly large) range of
roomtemperature resistivity values reported for CoSi: 180 mWcm for single-crystal CoSi and 2200mWcm for
polycrystalline CoSi.’
[72] N Ishigami, H Ago, T Nishi, K Ikeda, M
Tsuji, T Ikuta, and K Takahashi,
‘Unidirectional Growth of Single-Walled Carbon Nanotubes’, Journal of the American Chemical Society 130 17264–5 (2008)
‘The ratio of the forward SWNTs grown from
the sputtered catalysts (r < 80%) was lower than that originated by
the Co-Mo salt catalyst (96%). In the case of the sputtered catalyst, this
ratio increased with decreasing film thickness; when the film thickness was
decreased from 1.5 to 0.5 nm, the ratio increased from 65% to 74% for the Fe
film and 68% to 77% for the Co film. The perfect unidirectional growth was not
observed even for the very thin films with a thickness below 0.5 nm. The imperfect
unidirectional SWNT growth for the sputtered catalyst may be originated from
the damage of the surface atomic arrangement on the sapphire due to collision
of the sputtered high-energy atoms and/or the inhomogeneous particle size
distribution observed for the sputtered film . The length of the backward SWNTs
was found to be relatively shorter than that of the forward nanotubes,
suggesting that nanotube growth in the forward direction is more favorable than
the backward direction.’
[73] J Sharma, R Chhabra, C S Andersen, K V
Gothelf, H Yan and Y Liu, ‘ Toward Reliable Gold Nanoparticle Patterning On
Self-Assembled DNA Nanoscaffold’, Journal of the American Chemical Society
130 7820-1 (2008)
Organizing metallic nanoparticles in a
well-controlled manner is of great interest for nanophotonics and
nanoelectronics applications1 Toward this goal, DNA-directed assembly has shown
great progress in constructing one-dimensional, two-dimensional, and discrete
gold nanoparticle (AuNP) architectures. One common strategy to obtain such
structures was to first link a DNA molecule carrying a monothiol modification
to AuNP and subsequently use the sequence information of DNA to control the
positioning of the AuNP-DNA conjugates onto DNA scaffolds. Very often the
structure achieved suffered from low yield partly because of the limited
strength of the linkage between the AuNP surface and the monothiol functionalized
DNA molecules, and also because of competitive binding of other ligands during
surface passivations.’
[74] L Zhang, S Zaric, X Tu, X Wang, W Zhao and
H Dai, ‘Assessment of Chemically Separated Carbon Nanotubes for Nanoelectronics’,
Journal of the American Chemical Society
130 2686–2691 (2008)
‘It remains an elusive goal to obtain high
performance single-walled carbon-nanotube (SWNT) electronics such as field
effect transistors (FETs) composed of single- or few-chirality SWNTs, due to
broad distributions in as-grown materials. Much progress has been made by
various separation approaches to obtain materials enriched in metal or
semiconducting nanotubes or even in single chiralties. However, research in
validating SWNT separations by electrical transport measurements and building
functional electronic devices has been scarce.’
[75] Y Song, A L Schmitt and S Jin, ‘Ultralong
Single-Crystal Metallic Ni2Si Nanowires with Low Resistivity, Nano Letters 7 965-9 (2007)
‘If the challenges of large-scale
hierarchical assembly and precise positioning of NWs can be satisfactorily
addressed, nanoscale building blocks of low-resistivity single-crystal metallic
materials with a suitable work function such as Ni2Si will serve as superior interconnects
and gate nanowires for crossed NW nanoelectronic architectures.’
[76] A Ismach and E Joselevich, ‘Orthogonal
Self-Assembly of Carbon Nanotube Crossbar Architectures by Simultaneous
Graphoepitaxy and Field-Directed Growth’, Nano
Letters 6 1706-10 (2006)
A statistical analysis of the nanotube
orientation in a dense orthogonally self-assembled crossbar array is displayed
in Figure. The angular distribution of the nanotubes (relative to the step
vector s) between the electrodes is bimodal with two well-resolved peaks
at 4±8° and 100±8°, which
correspond to the directions of the nanosteps and the applied electric field, respectively.
Far away from the electrodes where the influence of the electric field is very
weak and no SiO2 was deposited, the angular distribution shows a single peak at
1.2 ± 4°, indicating that all the nanotubes have grown along
the nanosteps. Figure x shows the distribution of crossing angles between the
nanotubes at the crossbar junctions, showing a normal distribution of 96±12°. Cross densities of typically 7, and up to 12 per μm2
were found on these samples.
[77] C Daraio, V F Nesterenko, J F Aubuchon
and S Jin, ‘Dynamic Nanofragmentation of Carbon Nanotubes’ Nano Letters 4
1915-8 (2004)
‘For example, nanoelectronics, nanocircuit interconnections, nanooptics
(nano laser array), NEMS (nanoelectromechanical systems) devices including
nanomanipulators, AFM tips, biomedical applications for interaction with DNAs,
sensors, actuators, and so forth require a controlled and manageable length,
rather than the often uncontrollably long nanotubes. Some applications require
opening of nanotubes especially for filling the inside with other materials or
for chemically functionalizing the open ends for advanced composites or for
biochemical conjugations. At least one end is usually closed in the
assynthesized nanotubes as the growing nanotube tip is terminated with either a
dome or a catalyst particle. Cutting or opening of nanotubes is typically
carried out by etching with concentrated acids, such as nitric acid, or by
mechanical grinding. However, most of these processes result in uncontrolled
cut lengths and often cause structural damage such as amorphization or
disrupted nanotube walls. Furthermore, none of these methods allows convenient
cutting into nanoscale lengths of 100-200 nm.’
[78] G F Close, S Yasuda, B Paul, S Fujita,
and H-S P Wong, ‘A 1 GHz Integrated Circuit with Carbon Nanotube Interconnects
and Silicon Transistors’ Nano Letters
8 706-9 (2008)
‘The key in achieving GHz operation with
individual MWCNT interconnects, and more generally any individual
nanoelectronic devices/structures, is to have a chain of fast circuits spanning
all length scales from the nanoscale all the way up to the macroscopic test instruments
(Figure 4c). Conventional microelectronic circuits in silicon CMOS technology
are natural choices in the middle of this chain because they bridge the gap
from the microscale to the macroscopic scale. Without this intermediate CMOS
link, individual nanoscale devices would not be able to effectively drive any
macroscopic circuits at GHz frequencies directly because of their low current
drive compared to the macroscopic parasitic capacitances. Our approach opens up
the possibility of in situ GHz benchmarking of nanoelectronic devices in a
silicon environment.’
[79] H Shimawakia, K Murakami, Y Neo, H
Mimura, F Wakaya and M Takai, ‘ Evaluation of emission uniformity of
nanocrystalline silicon planar cathodes, Journal
of Vacuum Science and Technology B 28 C2C49-52 (2010)
‘A planar-type cold cathode that has a thin
film diode structure, such as a metal-oxide-semiconductor tunneling cathode,
produces highly directional emission and is insensitive to environment in
contrast with a field emission cathode. The authors fabricated the planar
cathodes based on nanocrystalline silicon covered with a thin oxide film
prepared by pulsed laser ablation and examined the emission uniformity. The
electron emission from the cathode with thin gold metal occurred around the
edge of the emission area where it was surrounded with contact metal of thick
aluminum, while electrons were emitted near the center of the area in the
cathode with thin platinum. Afterward, the electron emitted area extended to
the whole emission area with increasing the gate voltage. Scanning electron
microscopy images showed discontinuous island structures of gold film and
continuous and dense of platinum. The results demonstrated that emission
uniformity was strongly dependent on morphology and resistance of thin metal.’
[80] R Z Zhan, J Chen, S Z Deng and N . Xub,
‘ Study of techniques for improving emission uniformity of gated CuO nanowire
field emitter arrays’, Journal of Vacuum
Science and Technology B 28 C2C45-8 (2010)
‘However, we notice that there are still
about 54% emitters that did not work after adopting the lift-off procedure.
This may be caused by the following reasons. First, the resistance layer of the
ballast layer is not high enough to eliminate all the variation in field
emission characteristics. Second, resistance of ballast layer former is not
uniform. Third, there is a difference in field emission characteristics of
nanowires. We will try to improve the uniformity by optimizing the resistance of
the resistive layer, adopting post-treatment, such as current conditioning or
plasma treatment in our further study.’
[81] V Joshi, A . Orlov and G L Snider, ‘Silicon
single-electron transistor with oxide tunnel barriers fabricated using chemical
mechanical polishing’, Journal of Vacuum
Science and Technology B 26 2587-91
(2008)
‘Silicon single-electron transistors (Si-SETs)
fabricated by various methods have been shown to have excellent charge stability
as compared to metal tunnel junction devices. Also by utilizing techniques
developed for very large scale integrated (VLSI) technology, one can make the
devices dimensionally smaller and hence operate at room temperature and above.
However, a majority of the devices reported so far suffer from a number of
problems due to poor control over the dot size and tunnel barrier thickness.
Furthermore, the randomness of the island formation reduces the yield of the
process, effectively precluding the use of these devices for most of the
practical applications.’
[82] G von
Freymann, T Y M Chan, S John, V Kitaev, G A Ozin, M Deubel and M Wegener, ‘Sub-nanometer
precision modification of the optical properties of three-dimensional
polymer-based photonic crystals’, Photonics
and Nanostructures – Fundamentals and Applications 2 191–198 (2004)
‘Scientists,
involved in the quest of making largescale three-dimensional (3D) photonic crystals
, have recently turned their attention to templating 3D photonic crystals using
polymer materials. Lithographic techniques like laser holography and direct
laser writing [5,6] allow for the fabrication of 3D photonic crystals up to
square millimeter size without incorporating intrinsic defects, commonly found
when using colloidal templating techniques (see for a discussion of different
intrinsic defect types). These optical lithography methods, when used
incombination, allow for the incorporation of waveguides and resonators and
therefore enable direct templating of functional photonic devices. They have only
one drawback: the minimal size of structural features is connected to the
wavelength of the illuminating laser and/or limited by the resolution achievable
with the polymer materials. This limitation might hinder the direct use of
these templates for the fabrication of 3D photonic crystals at
telecommunication wavelengths via infiltration of high-index of refraction
materials like silicon. Therefore, a technique to overcome this limitation is
required but should not only yield the desired result but equally be suited for
mass production’
[83] S-H Lee, Y Jung, H-S Chung, A T
Jennings and R Agarwal, ‘Comparative study of memory-switching phenomena in
phase change GeTe and Ge2Sb2Te5 nanowire
devices’, Physica E 40 2474–80 (2008)
‘The memory-switching effect in phase change
chalcogenide materials is achieved by pulsed electric fields to induce Joule
heating, which leads to two distinct electronic states corresponding to
amorphous and crystalline phases. However, the realization of true potential of
these materials for memory applications still faces many technical challenges
owing to continued demand for high scalability with better structural
properties that is essential for memory devices operating with less power
consumption. Conventional top-down approach based on thin-film processes
involving multiple lithographic and etching steps often leads to structural degradation
of phase change materials and therefore may not provide viable solutions for
continued scaling down of device size. The bottom-up approach towards
assembling nanostructures as building blocks for electronic and photonic
devices is being intensively investigated as a potential solution to alleviate
the intrinsic problems of the top-down-based technology.’
[86] R Rinaldi and R Cingolani, ‘Electronic
nanodevices based on self-assembled metalloproteins’, Physica E 21 45 – 60 (2004)
‘We have demonstrated the 3rst
implementation of nprotein-based electronic nano-devices working in air and at
room temperature by using azurin metalloproteins. Both rectifying (diode-like)
and amplifying (transistor-like) devices have been implemented. Though this field
is still in its infancy, the results obtained so far are promising and deserve
further studies to determine the actual potentiality of these biodevices and to
elucidate a number of important issues,
such as the reproducibility and ageing of the nanodevices.’
[87]
S W D Bailey, I Amanatidis and C J Lambert, ‘Carbon Nanotube Electron Windmills: A Novel Design for Nanomotors’, Physical Review Letters 100, 256802 (2008)
‘Whereas
microfabricated motors, actuators and oscillators are typically manufactured by
conventional semiconductor processing techniques, their nanoscale counterparts
are more difficult to realize. ‘
[88] N P Oxtoby, H M Wiseman and H-B Sun, ‘Sensitivity
and back action in charge qubit measurements by a strongly coupled
single-electron transistor’, Physical
Review B 74 045328 (2006)
‘We reiterate that the derivation of Eq. (x)
requires that we work in the strong-coupling regime, where there is a large
difference between the qubit energy asymmetry for N=1 and that for N=0.
To achieve this would require careful manufacture of the SET as well as correct
choice of electrostatic gate voltages.’
[89] A La Magna, I Deretzis, G Forte and R
Pucci, ‘Conductance distribution in doped and defected graphene nanoribbons’, Physical Review B 80, 195413 (2009)
‘In this sense, the most promising systems
for graphene-based nanoelectronics are the graphene nanoribbons (GNRs), which
have been already synthesized by means of different pattering techniques.3,4 In
these cases, the control of the electronic properties is inherently related to
the accurate manipulation of the nanostructure edges. However, also the
chemical modification of the system bulk zone, e.g., using substitutional
impurities, has been proposed to overcome the minimum of conductivity problem.’
[90]
N M Zimmerma* and W H Huber, ‘Microscope of glassy relaxation in femtogram
samples: Charge offset drift in the single electron transistor’, Physical Review B 80 195304 (2009)
‘Recently, studies on nanoelectronic
devices, in general, have shown electrical characteristics which can depend on atomic
positions. These characteristics are generally considered to be “noise” which
arise from “defects” through either the defect position (atomic motion) or
charge state (charge traps). In addition to being unwanted noise, such
electrical measurements can also provide information about exquisitely small
ensembles of atomic motion, including the well known case of “two-level
fluctuators” (TLFs) which allow real-time measurements of the state of a single
microscopic defect.’
‘Single electron tunneling (SET) transistors
have excellent sensitivity when used as charge electrometers, with the ability to
measure capacitive charge changes below 10−4e. If there
is disordered material in the insulating regions surrounding the thin-film SET
transistor, any structural relaxation—if it is accompanied by a change in the
charge distribution of the defect—can give rise to a change in the capacitively
coupled “charge offset” Q0, which represents a (possibly time-dependent)
phase shift in the transistor control curve. In general, the resulting
fluctuations in transistor current fall into two regimes: standard 1/ f noise
(typical charge fluctuation about 0.001e) at short times, and large drift
(1e or greater) at times of hours or longer.’
[91] S S Datta, D R Strachan, A T C Johnson,
‘Gate coupling to nanoscale electronics,’ Physical
Review B 79, 205404 (2009)
‘To reduce the dimensions of three-terminal
devices to the single-molecule scale (well below 20 nm) requires that a number
of size-scaling issues be addressed. In particular, it is well known that for
ultrashort channels it becomes increasingly difficult to influence the channel
electrical conduction via the modulated potential of the gate electrode. Diminished gate coupling at the nanoscale has
already become an issue in the construction of carbon nanotube transistors, molecular
thin-film transistors, and
semiconducting nanowire devices. To
address this issue there has been interest in using ultrathin high-k dielectrics to increase the gate coupling as channel dimensions shrink
toward 20 nm. Yet on the much smaller molecular-scale (of order 1 nm), it is
still not clear how to most effectively couple the gate electrode to the
channel. It has also recently become
apparent that the possibility of unplanned tunnel and/or capacitive coupling to
metal particles or other contaminants is a serious concern for these devices.’
[92] B Varghese, Y Zhang, Y P Feng, C T Lim, and C-H Sow, ‘Probing the
size-structure-property correlation of individual nanowires’, Physical
Review B 79, 115419 (2009)
‘Advances in nanofabrication techniques
offered additional handles to tune material properties by altering the physical
size and shape of the nanomaterials. Physical properties of nanosized materials are
primarily determined by (i) spatial confinement effects, (ii) nature of the
surfaces, and (iii) its microstructural details. All these factors are
sensitively dependent on the characteristic size of the nanostructures. Most of
the “bottom up” nanofabrication approaches yield structures with a size distribution,
and hence the information obtained from the characterization of an array of
as-synthesized products gives rise to averaged results and does not reflect the
unique properties of individual nanostructures. In addition, physical
properties of every nanostructure are largely determined by its microstructure (e.g.,
crystal quality, type, and concentration density of defects).’
[93] L
Risch, ‘Pushing CMOS beyond the roadmap’,
Proceedings of ESSDERC, Grenoble,
France, 2005 63-8 (2005)
‘Compared to emerging research devices, e.g.
single electron, molecular or spin devices, only nanowires and Carbon nanotubes
promise similar device characteristics. But manufacturability and integration
in large scale still have to be proven. Therefore, today Si CMOS is the only
realistic approach for high density logic and memories. ‘
[94] V. Nosik, ‘Carbon Nanotubes and Si
Nanowires as an Alternative Route to Future Nanoelectronics’, IEEE Conference on Emerging Technologies –
Nanoelectronics 99-103 (2006)
‘These estimates open new horizons for
applications of CNTs as wires or 'vias' connecting the metallization layers in integrated
circuits. Unfortunately the presence of structural and substitution defects
could worsen the declared characteristics significantly, so the main obstacle
in the way of CNT electronic applications is still the reproducible
growthtechnology and quality control.’
[95] W Hoenlein, ‘Carbon Nanotubes for Potential Device and
Interconnect Applications’, 2006 IEEE
International Conference on Integrated
Circuit Design and Technology, ICICDT '06, 1-6 (2006)
‘The sorting and placement of the
nanostructures has not yet been
solved and will be the main challenge for nanotechnology in the future.’
[96] A V Melechko, V I Merkulov,
T E McKnight, M A Guillorn, K L Klein, D H Lowndes and M L Simpson, ‘Vertically aligned carbon nanofibers and
related structures: Controlled synthesis and directed assembly’, Journal of Applied Physics 97
041301 (2005)
‘Significant progress has been made to
achieve controlled synthesis and directed assembly of carbon nanostructures. However,
there is still a need for a process that operates at temperatures that can be
tolerated by a larger variety of substrate materials, yet provides greater
control of nanostructure properties. A better understanding of the fundamental
mechanisms of nanostructure nucleation and growth points the way for future
work. The key to the catalytic growth of carbon nanofibers is in the processes
that occur at the surface of or within the catalytic particle. Plasma
processing provides a way to control these processes via interaction with the
electromagnetic field. The electric field plays a crucial role in the alignment
control of carbon nanofibers by the coupling of mechanical force to the
synthesis process. High-frequency electromagnetic fields, augmented by field
enhancement at the tip of a nanofiber, may be the way to control the
temperature of the catalyst separately from the substrate. Another major
challenge is the precise control of the nanofiber structure. The growth of
isolated single vertically aligned carbon nanotubes, mulitwalled or
singlewalled, is yet to be demonstrated. We are just beginning to gain an
understanding of the processes that control the arrangement of graphene layers
of a growing nanostructure. The relation of a carbon nanofiber structure and
catalyst particle shape, crystallographic orientation, and their dynamics will
eventually be understood and an additional level of control of synthesis will
be achieved, bringing future possibilities for practical nanoscale devices due
to improved characteristics.’
[97] M Zhou, R Li, J Zhou, X Guo, B Liu, Z
Zhang, and E Xie, ‘Growth and
characterization of aligned ultralong and diameter-controlled silicon nanotubes
by hot wire chemical vapor deposition using electrospun poly (vinyl pyrrolidone)
nanofiber template’, Journal of Applied Physics 106, 124315 (2009)
‘The preparation of silicon tubular
nanostructures remains a challenge because of the preference for sp3
hybridization in silicon, which promotes the formation of SiNWs rather than nanotubes.
It was reported that SiNTs have been prepared by a chemical vapor deposition (CVD)
process using nanochannel Al2O3 (NCA) substrate or on porous alumina using
molecular beam epitaxy. However, once the templates were removed, these tubes
would generally bundle up and became less oriented, even damaged. Meanwhile,
these templates were not suitable for the preparation of sufficiently long
tubes due to insurmountable difficulties in template fabrication. Therefore,
considerable efforts have also been made to prepare aligned ultralong
nanotubes, which are motivated by their high functionality in advanced thin
film devices.’
[98]
A Miura, Y Uraoka, T Fuyuki, S Yoshii, and I Yamashita, ‘Floating nanodot gate
memory fabrication with biomineralized nanodot’, Journal of Applied Physics, 103, 074503 (2008)
‘The
performance and the success of floating nanodot gate memories strongly depend
on the structural characteristics of fabricated nanodots such as size, shape,
and in-plane ordering and density of them in the MOS stacked structure.
Therefore, highdensity array of monodisperse and homogeneous nanodots is needed.
However, uniform and well-ordered high-density nanodot array fabrication on the
desired small area is still a difficult issue with conventional methods.’
[99] S Lastella, G Mallick, R Woo, and S P
Karnac, D A Rider, I Manners, Y J Jung,
C Y Ryu and P M. Ajayan, ‘Parallel arrays of individually addressable
single-walled carbon nanotube field-effect transistors,’ Journal of Applied
Physics 99, 024302 (2006)
‘Assembly and fabrication of SWNT electronic
devices still require several tedious steps just to realize a single or few
functional devices, which do not conveniently lend themselves to high-yield
productions.’
[100] J H Lee, Z M Wang, V G Dorogan, Y I
Mazur, M E Ware and G J Salamo, ‘Tuning the emission profiles of various
self-assembled InxGa1−xAs nanostructures by rapid thermal
annealing’, Journal of Applied Physics 106, 073106 (2009)
‘From an application standpoint, emission
tunability and enhanced optical properties of nanostructures are important in
order to improve the performance and sensitivity of optoelectronic devices:
i.e., a desired wavelength and a narrow full width at half maximum (FWHM). To
achieve these desired properties, numerous research efforts have been
dedicated. These include the control of size, density, dimension, configuration,
and position of nanostructure and the improvement of material quality by
modifying the growth processes. Although it is, in most cases, the only option,
improving optical properties and nanostructure quality by the modification of
growth parameters and fabrication processes is still time consuming, costly,
and painstaking. Fortunately, in some cases, we can use some of the postgrowth
procedures.’
[101] T Kantoa and K Yamaguchi, ‘In-plane
self-arrangement of high-density InAs quantum dots on GaAsSb/GaAs(001) by
molecular beam epitaxy, Journal of Applied Physics 101,
094901 (2007)
‘However, in the case of SK growth of a
single QD layer on a conventional (001) substrate, in-plane arrangement of QDs
is more difficult, and QDs are randomly .ilformed on the (001) surface.
Furthermore, high QD density and high uniformity in the QD structure are needed
for fabrication of in-plane arranged QDs. However, improvement in size
uniformity yields a low QD density because of the long migration length.’
[102]
M Sarikaya, C Tamerler, A K-Y Jen and K Schulten, ‘Molecular biomimetics:
nanotechnology through biology’, Nature
Materials 2 577-85 (2003)
‘Nanometre-sized particles and
nanostructured inorganics could be fundamental building blocks for future technological
materials and devices. Numerous challenges must be addressed before they are
successfully implemented into working systems. These include synthesizing nanostructures (for
example, particles, rods and tubes) with uniform size and shape, controlling their mineralogy, surface structures and chemistry, and predicting their
spatial distribution.